Decreasing Simulation Regression Turnaround Time With Dynamic Efficiency Optimization

No single step within the growth of semiconductor gadgets is extra delicate to hurry than useful simulation. A contemporary system-on-chip (SoC) design simulates billions of cycles of operation within the technique of finishing the verification plan and reaching protection objectives. To validate full system performance, many of those simulations embrace operating code on a number of embedded processors. Even pure {hardware} simulation assessments are resource-intensive because of the dimension and complexity of the chip. Accordingly, something that may be achieved to hurry up simulation and scale back the turnaround time (TAT) for each particular person assessments and the general regression suite is extremely useful.

Verification engineers are prepared to commit quite a lot of effort to optimizing the testbench and assessments to lower runtime, even when solely by just a few proportion factors. They make the most of the cloud, compute grids, and multi-core machines to parallelize as a lot of the regressions as attainable. Additionally they spend important effort in hand-tuning simulation parameters to reduce TAT. Whereas all this work is taken into account worthwhile because of the payback, it consumes treasured human sources throughout a vital part of the undertaking. This white paper presents an alternate strategy that automates key features of optimizing simulation efficiency and decreasing TAT. That is a necessary step in SoC growth, and it supplies worth for smaller chip tasks as nicely.

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