New Cadence Certus Delivers As much as 10X Quicker Concurrent Full-Chip Optimization and Signoff

SAN JOSE, Calif.— October 12, 2022 — Cadence Design Methods, Inc. (Nasdaq: CDNS) as we speak introduced the brand new Cadence^® Certus^™ Closure Resolution to handle rising chip-level design dimension and complexity challenges. The Cadence Certus Closure Resolution setting automates and accelerates the whole design closure cycle from weeks to in a single day—from signoff optimization via routing, static timing evaluation (STA) and extraction. The answer helps the most important chip design tasks with limitless capability whereas considerably enhancing productiveness by as much as 10X versus present methodologies and flows.

The Cadence Certus Closure Resolution eases the design signoff closure bottlenecks and complexities that include creating as we speak’s rising purposes like hyperscale computing, 5G communications, cell, automotive and networking. Previous to the introduction of the Cadence Certus Closure Resolution, a full-chip closure movement concerned guide, tedious processes from full chip meeting, static timing evaluation, and optimization and signoff with 100s of views, taking designers months to converge. The brand new resolution offers a totally automated setting that’s massively distributed for superior optimization and signoff. This permits concurrent, full-chip optimization via an engine shared with Cadence’s Innovus^™ Implementation System and the Tempus^™ Timing Signoff Resolution, eliminating iterative loops with block house owners whereas enabling designers to make fast optimization and signoff selections. Moreover, at the side of the Cadence Cerebrus^™ Clever Chip Explorer, designers can expertise extra productiveness enhancements from block-level to full-chip signoff closure.

The Cadence Certus Closure Resolution offers prospects with the next advantages:

• Revolutionary scalable structure: The Cadence Certus Closure Resolution’s distributed hierarchical optimization and signoff structure is good for cloud-execution and is operational in each cloud and inside knowledge middle environments
• Incremental signoff: Gives versatile restore and alternative of solely the modified parts of the design, additional accelerating remaining signoff
• Improved engineering productiveness: Absolutely automated flowreducesthe want for a number of, prolonged iterations throughout a number of groups, offering sooner time-to-market
• SmartHub interface: Enhanced interactive GUI permits cross-probing for detailed timing debug to drive last-mile design closure
• 3D-IC design efficiencies: Tightly built-in with the Cadence Integrity^™ 3D-IC Resolution, it permits customers to shut inter-die paths throughout heterogenous course of dies

“At the moment’s design groups usually spend 5 to seven days per iteration to satisfy chip-level signoff timing and energy necessities, and former methodologies did not ship the staff collaboration and consumer expertise wanted for environment friendly design closure,” stated Dr. Chin-Chi Teng, senior vice chairman and common supervisor within the Digital & Signoff Group at Cadence. “We’re intensely in tune with the wants of the design group, and with the discharge of the brand new Cadence Certus Closure Resolution, we’re providing our prospects a novel setting for chip-level optimization and signoff that delivers distinctive PPA outcomes inside a matter of hours. With this new Cadence resolution, we’re empowering prospects to realize productiveness targets and ship merchandise to market sooner.”

The Cadence Certus Closure Resolution helps the corporate’s Clever System Design^™ technique, which allows design excellence. For extra data, please go to www.cadence.com/go/certuspr.

Buyer Endorsements

“It’s crucial for us to ship our high-performance and low-power analog and mixed-signal merchandise on schedule. Full chip-level signoff closure is likely one of the largest bottlenecks our engineering staff faces when working tirelessly to satisfy buyer supply commitments. With the Cadence Certus Closure Resolution, our engineering staff can expertise in a single day full chip-level signoff closure by way of its concurrent optimization and signoff capabilities, enhancing total engineering staff productiveness. The answer’s skill to automate the entire optimization and signoff movement—STA, routing, and extraction—empowers our engineering staff to realize significantly improved design success, notice untapped energy financial savings of as much as 5% and get to market sooner.”
-Dr. Paolo Miliozzi, vice chairman, SoC Design and Expertise, MaxLinear

“In as we speak’s dynamic design setting, we require automated and sturdy signoff closure methodologies and instruments to satisfy time-to-market aims. With the Cadence Certus Closure Resolution, our engineering staff noticed 6X sooner chip-level signoff closure turnaround time versus present methodologies, enhancing total productiveness. Following this success, we plan to undertake the answer for the event of our newest designs.”
–Yukio Minoda, Senior Principal Engineer, Digital Design Expertise Division, Shared R&D EDA Division, Renesas

About Cadence

Cadence is a pivotal chief in digital programs design, constructing upon greater than 30 years of computational software program experience. The corporate applies its underlying Clever System Design technique to ship software program, {hardware} and IP that flip design ideas into actuality. Cadence prospects are the world’s most revolutionary firms, delivering extraordinary digital merchandise from chips to boards to finish programs for essentially the most dynamic market purposes, together with hyperscale computing, 5G communications, automotive, cell, aerospace, shopper, industrial and healthcare. For eight years in a row, Fortune journal has named Cadence one of many 100 Finest Corporations to Work For. Be taught extra at cadence.com.