Cadence Permits 10x Quicker Concurrent Full-chip Optimization and Signoff

Cadence Design Methods Inc.’s Certus Closure Answer addresses the rising chip-level design measurement and complexity challenges by automating and accelerating the whole design closure cycle from weeks to in a single day—from signoff optimization via routing, static timing evaluation (STA) and extraction. The answer helps the most important chip design initiatives with limitless capability whereas considerably enhancing productiveness by as much as 10x versus present methodologies and flows.

The Cadence Certus Closure Answer eases the design signoff closure bottlenecks and complexities that include creating right now’s rising purposes like hyperscale computing, 5G communications, cell, automotive and networking. Previous to the introduction of the answer, a full-chip closure movement concerned handbook, tedious processes from full chip meeting, static timing evaluation, and optimization and signoff with 100s of views, taking designers months to converge. The brand new resolution supplies a totally automated atmosphere that’s massively distributed for superior optimization and signoff. This permits concurrent, full-chip optimization via an engine shared with Cadence’s Innovus Implementation System and the Tempus Timing Signoff Answer, eliminating iterative loops with block homeowners whereas enabling designers to make fast optimization and signoff selections. Moreover, together with the Cadence Cerebrus Clever Chip Explorer, designers can expertise extra productiveness enhancements from block-level to full-chip signoff closure.

The Cadence Certus Closure Answer supplies prospects with modern scalable structure, incremental signoff, improved engineering productiveness, SmartHub interface, and 3D-IC design efficiencies.

“Right now’s design groups usually spend 5 to seven days per iteration to satisfy chip-level signoff timing and energy necessities, and former methodologies didn’t ship the crew collaboration and person expertise wanted for environment friendly design closure,” mentioned Dr. Chin-Chi Teng, senior vice chairman and normal supervisor within the Digital & Signoff Group at Cadence. “We’re intensely in tune with the wants of the design group, and with the discharge of the brand new Cadence Certus Closure Answer, we’re providing our prospects a novel atmosphere for chip-level optimization and signoff that delivers distinctive PPA outcomes inside a matter of hours. With this new Cadence resolution, we’re empowering prospects to realize productiveness objectives and ship merchandise to market sooner.”

The Cadence Certus Closure Answer helps the corporate’s Clever System Design technique, which permits design excellence.