New Cadence Certus Delivers As much as 10X Sooner Concurrent Full-Chip Optimization and Signoff

SAN JOSE, Calif.–(BUSINESS WIRE)–Cadence Design Techniques, Inc. (Nasdaq: CDNS) as we speak introduced the brand new Cadence^® Certus^™ Closure Answer to handle rising chip-level design dimension and complexity challenges. The Cadence Certus Closure Answer surroundings automates and accelerates the whole design closure cycle from weeks to in a single day—from signoff optimization by routing, static timing evaluation (STA) and extraction. The answer helps the most important chip design initiatives with limitless capability whereas considerably enhancing productiveness by as much as 10X versus present methodologies and flows.

The Cadence Certus Closure Answer eases the design signoff closure bottlenecks and complexities that include creating as we speak’s rising functions like hyperscale computing, 5G communications, cellular, automotive and networking. Previous to the introduction of the Cadence Certus Closure Answer, a full-chip closure move concerned guide, tedious processes from full chip meeting, static timing evaluation, and optimization and signoff with 100s of views, taking designers months to converge. The brand new answer offers a completely automated surroundings that’s massively distributed for superior optimization and signoff. This permits concurrent, full-chip optimization by an engine shared with Cadence’s Innovus^™ Implementation System and the Tempus^™ Timing Signoff Answer, eliminating iterative loops with block house owners whereas enabling designers to make fast optimization and signoff choices. Moreover, along side the Cadence Cerebrus^™ Clever Chip Explorer, designers can expertise further productiveness enhancements from block-level to full-chip signoff closure.

The Cadence Certus Closure Answer offers clients with the next advantages:

• Progressive scalable structure: The Cadence Certus Closure Answer’s distributed hierarchical optimization and signoff structure is right for cloud-execution and is operational in each cloud and inner information middle environments
• Incremental signoff: Offers versatile restore and substitute of solely the modified parts of the design, additional accelerating ultimate signoff
• Improved engineering productiveness: Absolutely automated move reduces the necessity for a number of, prolonged iterations throughout a number of groups, offering quicker time-to-market
• SmartHub interface: Enhanced interactive GUI permits cross-probing for detailed timing debug to drive last-mile design closure
• 3D-IC design efficiencies: Tightly built-in with the Cadence Integrity^™ 3D-IC Answer, it permits customers to shut inter-die paths throughout heterogenous course of dies

“In the present day’s design groups usually spend 5 to seven days per iteration to satisfy chip-level signoff timing and energy necessities, and former methodologies didn’t ship the crew collaboration and person expertise wanted for environment friendly design closure,” stated Dr. Chin-Chi Teng, senior vp and basic supervisor within the Digital & Signoff Group at Cadence. “We’re intensely in tune with the wants of the design group, and with the discharge of the brand new Cadence Certus Closure Answer, we’re providing our clients a novel surroundings for chip-level optimization and signoff that delivers distinctive PPA outcomes inside a matter of hours. With this new Cadence answer, we’re empowering clients to attain productiveness targets and ship merchandise to market quicker.”

The Cadence Certus Closure Answer helps the corporate’s Clever System Design^™ technique, which permits design excellence. For extra data, please go to www.cadence.com/go/certuspr.

Buyer Endorsements

“It’s crucial for us to ship our high-performance and low-power analog and mixed-signal merchandise on schedule. Full chip-level signoff closure is among the greatest bottlenecks our engineering crew faces when working tirelessly to satisfy buyer supply commitments. With the Cadence Certus Closure Answer, our engineering crew can expertise in a single day full chip-level signoff closure through its concurrent optimization and signoff capabilities, enhancing total engineering crew productiveness. The answer’s potential to automate the entire optimization and signoff move—STA, routing, and extraction—empowers our engineering crew to attain significantly improved design success, notice untapped energy financial savings of as much as 5% and get to market quicker.”

-Dr. Paolo Miliozzi, vp, SoC Design and Know-how, MaxLinear

“In as we speak’s dynamic design surroundings, we require automated and strong signoff closure methodologies and instruments to satisfy time-to-market targets. With the Cadence Certus Closure Answer, our engineering crew noticed 6X quicker chip-level signoff closure turnaround time versus present methodologies, enhancing total productiveness. Following this success, we plan to undertake the answer for the event of our newest designs.”

–Yukio Minoda, Senior Principal Engineer, Digital Design Know-how Division, Shared R&D EDA Division, Renesas

About Cadence

Cadence is a pivotal chief in digital programs design, constructing upon greater than 30 years of computational software program experience. The corporate applies its underlying Clever System Design technique to ship software program, {hardware} and IP that flip design ideas into actuality. Cadence clients are the world’s most revolutionary firms, delivering extraordinary digital merchandise from chips to boards to finish programs for probably the most dynamic market functions, together with hyperscale computing, 5G communications, automotive, cellular, aerospace, client, industrial and healthcare. For eight years in a row, Fortune journal has named Cadence one of many 100 Finest Corporations to Work For. Be taught extra at cadence.com.

© 2022 Cadence Design Techniques, Inc. All rights reserved worldwide. Cadence, the Cadence brand and the opposite Cadence marks discovered at www.cadence.com/go/logos are logos or registered logos of Cadence Design Techniques, Inc. All different logos are the property of their respective house owners.

Class: Featured